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ac: add rbplus_allowed to ac_gpu_info

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Samuel Pitoiset
2019-08-21 11:32:25 +02:00
parent 20c5db02b5
commit 021feb1bf6
10 changed files with 17 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/amd/common/ac_gpu_info.c
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@@ -457,6 +457,16 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->has_rbplus = info->family == CHIP_STONEY ||
info->chip_class >= GFX9;
/* Some chips have RB+ registers, but don't support RB+. Those must
* always disable it.
*/
info->rbplus_allowed = info->has_rbplus &&
(info->family == CHIP_STONEY ||
info->family == CHIP_VEGA12 ||
info->family == CHIP_RAVEN ||
info->family == CHIP_RAVEN2 ||
info->family == CHIP_RENOIR);
info->has_out_of_order_rast = info->chip_class >= GFX8 &&
info->max_se >= 2;

1
src/amd/common/ac_gpu_info.h
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@@ -62,6 +62,7 @@ struct radeon_info {
bool has_distributed_tess;
bool has_dcc_constant_encode;
bool has_rbplus; /* if RB+ registers exist */
bool rbplus_allowed; /* if RB+ is allowed */
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
bool cpdma_prefetch_writes_memory;

2
src/amd/vulkan/radv_cmd_buffer.c
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@@ -988,7 +988,7 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
static void
radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
{
if (!cmd_buffer->device->physical_device->rbplus_allowed)
if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
return;
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;

9
src/amd/vulkan/radv_device.c
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@@ -354,15 +354,6 @@ radv_physical_device_init(struct radv_physical_device *device,
radv_get_driver_uuid(&device->driver_uuid);
radv_get_device_uuid(&device->rad_info, &device->device_uuid);
if (device->rad_info.family == CHIP_STONEY ||
device->rad_info.chip_class >= GFX9) {
device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
device->rad_info.family == CHIP_VEGA12 ||
device->rad_info.family == CHIP_RAVEN ||
device->rad_info.family == CHIP_RAVEN2 ||
device->rad_info.family == CHIP_RENOIR;
}
device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
!(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);

2
src/amd/vulkan/radv_pipeline.c
View File

@@ -4055,7 +4055,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
z_order = V_02880C_LATE_Z;
bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
!device->physical_device->rbplus_allowed;
!device->physical_device->rad_info.rbplus_allowed;
/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
* but this appears to break Project Cars (DXVK). See

2
src/amd/vulkan/radv_private.h
View File

@@ -280,8 +280,6 @@ struct radv_physical_device {
int master_fd;
struct wsi_device wsi_device;
bool rbplus_allowed; /* if RB+ is allowed */
bool out_of_order_rast_allowed;
/* Whether DCC should be enabled for MSAA textures. */

14
src/gallium/drivers/radeonsi/si_pipe.c
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@@ -1173,20 +1173,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
*/
sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
/* Some chips have RB+ registers, but don't support RB+. Those must
* always disable it.
*/
if (sscreen->info.family == CHIP_STONEY ||
sscreen->info.chip_class >= GFX9) {
sscreen->rbplus_allowed =
!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
(sscreen->info.family == CHIP_STONEY ||
sscreen->info.family == CHIP_VEGA12 ||
sscreen->info.family == CHIP_RAVEN ||
sscreen->info.family == CHIP_RAVEN2 ||
sscreen->info.family == CHIP_RENOIR);
}
sscreen->dcc_msaa_allowed =
!(sscreen->debug_flags & DBG(NO_DCC_MSAA));

1
src/gallium/drivers/radeonsi/si_pipe.h
View File

@@ -511,7 +511,6 @@ struct si_screen {
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;
bool rbplus_allowed; /* if RB+ is allowed */
bool dcc_msaa_allowed;
struct slab_parent_pool pool_transfers;

6
src/gallium/drivers/radeonsi/si_state.c
View File

@@ -131,7 +131,7 @@ static void si_emit_cb_render_state(struct si_context *sctx)
}
/* RB+ register settings. */
if (sctx->screen->rbplus_allowed) {
if (sctx->screen->info.rbplus_allowed) {
unsigned spi_shader_col_format =
sctx->ps_shader.cso ?
sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
@@ -640,7 +640,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
color_control |= S_028808_MODE(V_028808_CB_DISABLE);
}
if (sctx->screen->rbplus_allowed) {
if (sctx->screen->info.rbplus_allowed) {
/* Disable RB+ blend optimizations for dual source blending.
* Vulkan does this.
*/
@@ -1483,7 +1483,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
if (sctx->screen->info.has_rbplus &&
!sctx->screen->rbplus_allowed)
!sctx->screen->info.rbplus_allowed)
db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,

2
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@@ -3992,7 +3992,7 @@ bool si_update_shaders(struct si_context *sctx)
si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
}
if (sctx->screen->rbplus_allowed &&
if (sctx->screen->info.rbplus_allowed &&
si_pm4_state_changed(sctx, ps) &&
(!old_ps ||
old_spi_shader_col_format !=