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turnip: implement depthBounds

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Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5628>
This commit is contained in:
Jonathan Marek
2020-06-23 18:45:32 -04:00
committed by Marge Bot
parent a9d866910c
commit 01e2893cba
3 changed files with 17 additions and 6 deletions
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8
src/freedreno/vulkan/tu_cmd_buffer.c
View File

@@ -971,8 +971,6 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_Z_BOUNDS_MIN, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_Z_BOUNDS_MAX, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
@@ -2326,6 +2324,12 @@ tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
float minDepthBounds,
float maxDepthBounds)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3);
tu_cs_emit_regs(&cs,
A6XX_RB_Z_BOUNDS_MIN(minDepthBounds),
A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds));
}
static void

2
src/freedreno/vulkan/tu_device.c
View File

@@ -595,7 +595,7 @@ tu_GetPhysicalDeviceFeatures(VkPhysicalDevice physicalDevice,
.depthClamp = true,
.depthBiasClamp = false,
.fillModeNonSolid = false,
.depthBounds = false,
.depthBounds = true,
.wideLines = false,
.largePoints = false,
.alphaToOne = true,

13
src/freedreno/vulkan/tu_pipeline.c
View File

@@ -1629,14 +1629,12 @@ tu6_emit_depth_control(struct tu_cs *cs,
const VkPipelineDepthStencilStateCreateInfo *ds_info,
const VkPipelineRasterizationStateCreateInfo *rast_info)
{
assert(!ds_info->depthBoundsTestEnable);
uint32_t rb_depth_cntl = 0;
if (ds_info->depthTestEnable) {
rb_depth_cntl |=
A6XX_RB_DEPTH_CNTL_Z_ENABLE |
A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
if (rast_info->depthClampEnable)
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
@@ -1645,6 +1643,9 @@ tu6_emit_depth_control(struct tu_cs *cs,
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
}
if (ds_info->depthBoundsTestEnable)
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
tu_cs_emit(cs, rb_depth_cntl);
}
@@ -2245,6 +2246,12 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
tu_cs_emit_regs(&cs,
A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
}
if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
.bfmask = ds_info->back.compareMask & 0xff));