From 012ff791fb842912c4b96d9ca730878abcddad31 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Tue, 20 Jun 2023 21:48:44 -0700 Subject: [PATCH] anv: Fix AUX-TT invalidation In order to make sure RCS engine is idle, we need to add DC flush + CS stall + Render target Cache flush + Depth Cache on Gfx 12 and additional CCS cache flush on Gfx12.5. Signed-off-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index eed52b0d79c..2a3366b0a39 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1489,7 +1489,8 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) { bits |= (ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT | ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_STATE_CACHE_INVALIDATE_BIT); + ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | + (GFX_VERx10 == 125 ? ANV_PIPE_CCS_CACHE_FLUSH_BIT: 0)); } /* If we're going to do an invalidate and we have a pending end-of-pipe