radv,aco: move radv_ps_epilog_key to the graphics pipeline key
To avoid redundant structs. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20199>
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@@ -2215,12 +2215,12 @@ radv_remove_color_exports(const struct radv_pipeline_key *pipeline_key, nir_shad
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if (idx < 0)
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continue;
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unsigned col_format = (pipeline_key->ps.spi_shader_col_format >> (4 * idx)) & 0xf;
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unsigned col_format = (pipeline_key->ps.epilog.spi_shader_col_format >> (4 * idx)) & 0xf;
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unsigned cb_target_mask = (pipeline_key->ps.cb_target_mask >> (4 * idx)) & 0xf;
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if (col_format == V_028714_SPI_SHADER_ZERO ||
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(col_format == V_028714_SPI_SHADER_32_R && !cb_target_mask &&
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!pipeline_key->ps.mrt0_is_dual_src)) {
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!pipeline_key->ps.epilog.mrt0_is_dual_src)) {
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/* Remove the color export if it's unused or in presence of holes. */
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nir->info.outputs_written &= ~BITFIELD64_BIT(var->data.location);
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var->data.location = 0;
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@@ -2750,12 +2750,12 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
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}
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}
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key.ps.spi_shader_col_format = blend->spi_shader_col_format;
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key.ps.epilog.spi_shader_col_format = blend->spi_shader_col_format;
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key.ps.cb_target_mask = blend->cb_target_mask;
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key.ps.mrt0_is_dual_src = blend->mrt0_is_dual_src;
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key.ps.epilog.mrt0_is_dual_src = blend->mrt0_is_dual_src;
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if (device->physical_device->rad_info.gfx_level < GFX8) {
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key.ps.color_is_int8 = blend->col_format_is_int8;
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key.ps.color_is_int10 = blend->col_format_is_int10;
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key.ps.epilog.color_is_int8 = blend->col_format_is_int8;
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key.ps.epilog.color_is_int10 = blend->col_format_is_int10;
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}
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if (device->physical_device->rad_info.gfx_level >= GFX11 && state->ms) {
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key.ps.alpha_to_coverage_via_mrtz = state->ms->alpha_to_coverage_enable;
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@@ -2774,8 +2774,7 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
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key.ps.lower_discard_to_demote = true;
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if (device->instance->enable_mrt_output_nan_fixup)
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key.ps.enable_mrt_output_nan_fixup = blend->col_format_is_float32;
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key.ps.epilog.enable_mrt_output_nan_fixup = blend->col_format_is_float32;
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key.ps.force_vrs_enabled = device->force_vrs_enabled;
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@@ -3752,15 +3751,7 @@ radv_pipeline_create_ps_epilog(struct radv_graphics_pipeline *pipeline,
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if (pipeline->base.shaders[MESA_SHADER_FRAGMENT] &&
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pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog && !pipeline->ps_epilog) {
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struct radv_ps_epilog_key epilog_key = {
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.spi_shader_col_format = pipeline_key->ps.spi_shader_col_format,
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.color_is_int8 = pipeline_key->ps.color_is_int8,
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.color_is_int10 = pipeline_key->ps.color_is_int10,
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.enable_mrt_output_nan_fixup = pipeline_key->ps.enable_mrt_output_nan_fixup,
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.mrt0_is_dual_src = pipeline_key->ps.mrt0_is_dual_src,
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};
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pipeline->ps_epilog = radv_create_ps_epilog(device, &epilog_key);
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pipeline->ps_epilog = radv_create_ps_epilog(device, &pipeline_key->ps.epilog);
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if (!pipeline->ps_epilog)
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return false;
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}
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@@ -5601,15 +5592,7 @@ radv_graphics_lib_pipeline_init(struct radv_graphics_lib_pipeline *pipeline,
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struct radv_pipeline_key key =
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radv_generate_graphics_pipeline_key(&pipeline->base, pCreateInfo, state, &blend);
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struct radv_ps_epilog_key epilog_key = {
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.spi_shader_col_format = blend.spi_shader_col_format,
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.color_is_int8 = blend.col_format_is_int8,
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.color_is_int10 = blend.col_format_is_int10,
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.enable_mrt_output_nan_fixup = key.ps.enable_mrt_output_nan_fixup,
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.mrt0_is_dual_src = blend.mrt0_is_dual_src,
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};
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pipeline->base.ps_epilog = radv_create_ps_epilog(device, &epilog_key);
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pipeline->base.ps_epilog = radv_create_ps_epilog(device, &key.ps.epilog);
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if (!pipeline->base.ps_epilog)
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goto fail_layout;
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}
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