gallium: plumb context priority through to driver
Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
This commit is contained in:
@@ -417,6 +417,10 @@ The integer capabilities:
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* ``PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET``:
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* ``PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET``:
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Whether pipe_vertex_buffer::buffer_offset is treated as signed. The u_vbuf
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Whether pipe_vertex_buffer::buffer_offset is treated as signed. The u_vbuf
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module needs this for optimal performance in workstation applications.
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module needs this for optimal performance in workstation applications.
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* ``PIPE_CAP_CONTEXT_PRIORITY_MASK``: For drivers that support per-context
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priorities, this returns a bitmask of PIPE_CONTEXT_PRIORITY_x for the
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supported priority levels. A driver that does not support prioritized
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contexts can return 0.
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.. _pipe_capf:
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.. _pipe_capf:
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@@ -268,6 +268,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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/* Stream output. */
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/* Stream output. */
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@@ -339,6 +339,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_DRAW_INDIRECT:
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case PIPE_CAP_DRAW_INDIRECT:
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@@ -326,6 +326,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_MAX_VIEWPORTS:
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case PIPE_CAP_MAX_VIEWPORTS:
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@@ -364,6 +364,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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}
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}
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/* should only get here on unhandled cases */
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/* should only get here on unhandled cases */
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@@ -228,6 +228,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_VENDOR_ID:
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case PIPE_CAP_VENDOR_ID:
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@@ -280,6 +280,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_VENDOR_ID:
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case PIPE_CAP_VENDOR_ID:
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@@ -309,6 +309,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_VENDOR_ID:
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case PIPE_CAP_VENDOR_ID:
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@@ -250,6 +250,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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/* SWTCL-only features. */
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/* SWTCL-only features. */
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@@ -411,6 +411,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_DOUBLES:
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@@ -274,6 +274,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_POST_DEPTH_COVERAGE:
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case PIPE_CAP_POST_DEPTH_COVERAGE:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_NATIVE_FENCE_FD:
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case PIPE_CAP_NATIVE_FENCE_FD:
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@@ -315,6 +315,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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return 4;
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return 4;
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@@ -459,6 +459,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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}
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}
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@@ -346,6 +346,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_VENDOR_ID:
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case PIPE_CAP_VENDOR_ID:
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@@ -288,6 +288,7 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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/* Stream output. */
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/* Stream output. */
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@@ -248,6 +248,7 @@ vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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/* Geometry shader output, unsupported. */
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/* Geometry shader output, unsupported. */
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@@ -273,6 +273,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return 0;
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return 0;
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case PIPE_CAP_VENDOR_ID:
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case PIPE_CAP_VENDOR_ID:
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return 0x1af4;
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return 0x1af4;
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@@ -391,6 +391,15 @@ enum pipe_flush_flags
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*/
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*/
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#define PIPE_CONTEXT_PREFER_THREADED (1 << 3)
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#define PIPE_CONTEXT_PREFER_THREADED (1 << 3)
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/**
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* Create a high priority context.
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*/
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#define PIPE_CONTEXT_HIGH_PRIORITY (1 << 4)
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/**
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* Create a low priority context.
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*/
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#define PIPE_CONTEXT_LOW_PRIORITY (1 << 5)
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/**
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/**
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* Flags for pipe_context::memory_barrier.
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* Flags for pipe_context::memory_barrier.
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@@ -785,8 +794,20 @@ enum pipe_cap
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PIPE_CAP_TILE_RASTER_ORDER,
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PIPE_CAP_TILE_RASTER_ORDER,
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PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES,
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PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES,
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PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
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PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
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PIPE_CAP_CONTEXT_PRIORITY_MASK,
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};
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};
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/**
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* Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should
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* return a bitmask of the supported priorities. If the driver does not
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* support prioritized contexts, it can return 0.
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*
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* Note that these match __DRI2_RENDER_HAS_CONTEXT_PRIORITY_*
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*/
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#define PIPE_CONTEXT_PRIORITY_LOW (1 << 0)
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#define PIPE_CONTEXT_PRIORITY_MEDIUM (1 << 1)
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#define PIPE_CONTEXT_PRIORITY_HIGH (1 << 2)
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#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
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#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
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#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
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#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
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@@ -92,6 +92,8 @@ enum st_api_feature
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#define ST_CONTEXT_FLAG_RESET_NOTIFICATION_ENABLED (1 << 3)
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#define ST_CONTEXT_FLAG_RESET_NOTIFICATION_ENABLED (1 << 3)
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#define ST_CONTEXT_FLAG_NO_ERROR (1 << 4)
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#define ST_CONTEXT_FLAG_NO_ERROR (1 << 4)
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#define ST_CONTEXT_FLAG_RELEASE_NONE (1 << 5)
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#define ST_CONTEXT_FLAG_RELEASE_NONE (1 << 5)
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#define ST_CONTEXT_FLAG_HIGH_PRIORITY (1 << 6)
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#define ST_CONTEXT_FLAG_LOW_PRIORITY (1 << 7)
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/**
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/**
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* Reasons that context creation might fail.
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* Reasons that context creation might fail.
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@@ -57,7 +57,9 @@ dri_create_context(gl_api api, const struct gl_config * visual,
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unsigned allowed_flags = __DRI_CTX_FLAG_DEBUG |
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unsigned allowed_flags = __DRI_CTX_FLAG_DEBUG |
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__DRI_CTX_FLAG_FORWARD_COMPATIBLE |
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__DRI_CTX_FLAG_FORWARD_COMPATIBLE |
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__DRI_CTX_FLAG_NO_ERROR;
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__DRI_CTX_FLAG_NO_ERROR;
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unsigned allowed_attribs = __DRIVER_CONTEXT_ATTRIB_RELEASE_BEHAVIOR;
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unsigned allowed_attribs =
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__DRIVER_CONTEXT_ATTRIB_PRIORITY |
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__DRIVER_CONTEXT_ATTRIB_RELEASE_BEHAVIOR;
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const __DRIbackgroundCallableExtension *backgroundCallable =
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const __DRIbackgroundCallableExtension *backgroundCallable =
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screen->sPriv->dri2.backgroundCallable;
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screen->sPriv->dri2.backgroundCallable;
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@@ -112,6 +114,19 @@ dri_create_context(gl_api api, const struct gl_config * visual,
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if (ctx_config->flags & __DRI_CTX_FLAG_NO_ERROR)
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if (ctx_config->flags & __DRI_CTX_FLAG_NO_ERROR)
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attribs.flags |= ST_CONTEXT_FLAG_NO_ERROR;
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attribs.flags |= ST_CONTEXT_FLAG_NO_ERROR;
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if (ctx_config->attribute_mask & __DRIVER_CONTEXT_ATTRIB_PRIORITY) {
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switch (ctx_config->priority) {
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case __DRI_CTX_PRIORITY_LOW:
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attribs.flags |= ST_CONTEXT_FLAG_LOW_PRIORITY;
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break;
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case __DRI_CTX_PRIORITY_HIGH:
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attribs.flags |= ST_CONTEXT_FLAG_HIGH_PRIORITY;
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break;
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default:
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break;
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}
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}
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if ((ctx_config->attribute_mask & __DRIVER_CONTEXT_ATTRIB_RELEASE_BEHAVIOR)
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if ((ctx_config->attribute_mask & __DRIVER_CONTEXT_ATTRIB_RELEASE_BEHAVIOR)
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&& (ctx_config->release_behavior == __DRI_CTX_RELEASE_BEHAVIOR_NONE))
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&& (ctx_config->release_behavior == __DRI_CTX_RELEASE_BEHAVIOR_NONE))
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attribs.flags |= ST_CONTEXT_FLAG_RELEASE_NONE;
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attribs.flags |= ST_CONTEXT_FLAG_RELEASE_NONE;
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@@ -55,7 +55,13 @@ dri2_query_renderer_integer(__DRIscreen *_screen, int param,
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PIPE_TEXTURE_2D, 0,
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PIPE_TEXTURE_2D, 0,
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PIPE_BIND_RENDER_TARGET);
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PIPE_BIND_RENDER_TARGET);
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return 0;
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return 0;
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case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
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value[0] =
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screen->base.screen->get_param(screen->base.screen,
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PIPE_CAP_CONTEXT_PRIORITY_MASK);
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if (!value[0])
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return -1;
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return 0;
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default:
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default:
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return driQueryRendererIntegerCommon(_screen, param, value);
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return driQueryRendererIntegerCommon(_screen, param, value);
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}
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}
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@@ -880,6 +880,11 @@ st_api_create_context(struct st_api *stapi, struct st_manager *smapi,
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if (attribs->flags & ST_CONTEXT_FLAG_NO_ERROR)
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if (attribs->flags & ST_CONTEXT_FLAG_NO_ERROR)
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no_error = true;
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no_error = true;
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if (attribs->flags & ST_CONTEXT_FLAG_LOW_PRIORITY)
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ctx_flags |= PIPE_CONTEXT_LOW_PRIORITY;
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else if (attribs->flags & ST_CONTEXT_FLAG_HIGH_PRIORITY)
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ctx_flags |= PIPE_CONTEXT_HIGH_PRIORITY;
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pipe = smapi->screen->context_create(smapi->screen, NULL, ctx_flags);
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pipe = smapi->screen->context_create(smapi->screen, NULL, ctx_flags);
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if (!pipe) {
|
if (!pipe) {
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*error = ST_CONTEXT_ERROR_NO_MEMORY;
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*error = ST_CONTEXT_ERROR_NO_MEMORY;
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Reference in New Issue
Block a user