262 lines
8.7 KiB
C
262 lines
8.7 KiB
C
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include "anv_private.h"
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#include "genX_multisample.h"
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/* These are defined in anv_private.h and blorp_genX_exec.h */
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#undef __gen_address_type
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#undef __gen_user_data
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#undef __gen_combine_address
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#include "common/gen_l3_config.h"
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#include "blorp/blorp_genX_exec.h"
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static void *
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blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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return anv_batch_emit_dwords(&cmd_buffer->batch, n);
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}
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static uint64_t
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blorp_emit_reloc(struct blorp_batch *batch,
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void *location, struct blorp_address address, uint32_t delta)
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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assert(cmd_buffer->batch.start <= location &&
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location < cmd_buffer->batch.end);
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return anv_batch_emit_reloc(&cmd_buffer->batch, location,
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address.buffer, address.offset + delta);
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}
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static void
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blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
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struct blorp_address address, uint32_t delta)
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
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ss_offset, address.buffer, address.offset + delta);
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}
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static void *
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blorp_alloc_dynamic_state(struct blorp_batch *batch,
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enum aub_state_struct_type type,
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uint32_t size,
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uint32_t alignment,
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uint32_t *offset)
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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struct anv_state state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
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*offset = state.offset;
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return state.map;
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}
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static void
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blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
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unsigned state_size, unsigned state_alignment,
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uint32_t *bt_offset,
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uint32_t *surface_offsets, void **surface_maps)
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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uint32_t state_offset;
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struct anv_state bt_state =
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anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
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&state_offset);
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if (bt_state.map == NULL) {
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/* We ran out of space. Grab a new binding table block. */
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VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
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assert(result == VK_SUCCESS);
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/* Re-emit state base addresses so we get the new surface state base
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* address before we start emitting binding tables etc.
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*/
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anv_cmd_buffer_emit_state_base_address(cmd_buffer);
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bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
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&state_offset);
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assert(bt_state.map != NULL);
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}
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uint32_t *bt_map = bt_state.map;
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*bt_offset = bt_state.offset;
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for (unsigned i = 0; i < num_entries; i++) {
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struct anv_state surface_state =
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anv_cmd_buffer_alloc_surface_state(cmd_buffer);
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bt_map[i] = surface_state.offset + state_offset;
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surface_offsets[i] = surface_state.offset;
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surface_maps[i] = surface_state.map;
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}
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}
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static void *
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blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
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struct blorp_address *addr)
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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struct anv_state vb_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 16);
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*addr = (struct blorp_address) {
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.buffer = &cmd_buffer->device->dynamic_state_block_pool.bo,
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.offset = vb_state.offset,
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};
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return vb_state.map;
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}
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static void
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blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
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{
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struct anv_device *device = batch->blorp->driver_ctx;
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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genX(emit_urb_setup)(device, &cmd_buffer->batch,
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VK_SHADER_STAGE_VERTEX_BIT |
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VK_SHADER_STAGE_FRAGMENT_BIT,
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vs_entry_size, 0,
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cmd_buffer->state.current_l3_config);
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}
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static void
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blorp_emit_3dstate_multisample(struct blorp_batch *batch, unsigned samples)
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{
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blorp_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
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ms.NumberofMultisamples = __builtin_ffs(samples) - 1;
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#if GEN_GEN >= 8
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/* The PRM says that this bit is valid only for DX9:
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*
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* SW can choose to set this bit only for DX9 API. DX10/OGL API's
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* should not have any effect by setting or not setting this bit.
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*/
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ms.PixelPositionOffsetEnable = false;
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ms.PixelLocation = CENTER;
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#else
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ms.PixelLocation = PIXLOC_CENTER;
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switch (samples) {
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case 1:
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SAMPLE_POS_1X(ms.Sample);
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break;
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case 2:
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SAMPLE_POS_2X(ms.Sample);
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break;
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case 4:
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SAMPLE_POS_4X(ms.Sample);
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break;
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case 8:
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SAMPLE_POS_8X(ms.Sample);
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break;
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default:
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break;
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}
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#endif
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}
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}
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void genX(blorp_exec)(struct blorp_batch *batch,
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const struct blorp_params *params);
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void
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genX(blorp_exec)(struct blorp_batch *batch,
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const struct blorp_params *params)
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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if (!cmd_buffer->state.current_l3_config) {
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const struct gen_l3_config *cfg =
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gen_get_default_l3_config(&cmd_buffer->device->info);
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genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
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}
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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if (cmd_buffer->state.current_pipeline != _3D) {
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#if GEN_GEN <= 7
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/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
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* PIPELINE_SELECT [DevBWR+]":
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*
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* Project: DEVSNB+
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*
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* Software must ensure all the write caches are flushed through a
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* stalling PIPE_CONTROL command followed by another PIPE_CONTROL
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* command to invalidate read only caches prior to programming
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* MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
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*/
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blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
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pc.RenderTargetCacheFlushEnable = true;
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pc.DepthCacheFlushEnable = true;
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pc.DCFlushEnable = true;
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pc.PostSyncOperation = NoWrite;
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pc.CommandStreamerStallEnable = true;
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}
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blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
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pc.TextureCacheInvalidationEnable = true;
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pc.ConstantCacheInvalidationEnable = true;
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pc.StateCacheInvalidationEnable = true;
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pc.InstructionCacheInvalidateEnable = true;
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pc.PostSyncOperation = NoWrite;
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}
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#endif
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blorp_emit(batch, GENX(PIPELINE_SELECT), ps) {
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#if GEN_GEN >= 9
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ps.MaskBits = 3;
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#endif
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ps.PipelineSelection = _3D;
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}
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cmd_buffer->state.current_pipeline = _3D;
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}
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blorp_exec(batch, params);
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/* BLORP sets DRAWING_RECTANGLE but we always want it set to the maximum.
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* Since we set it once at driver init and never again, we have to set it
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* back after invoking blorp.
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*
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* TODO: BLORP should assume a max drawing rectangle
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*/
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blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
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rect.ClippedDrawingRectangleYMin = 0;
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rect.ClippedDrawingRectangleXMin = 0;
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rect.ClippedDrawingRectangleYMax = UINT16_MAX;
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rect.ClippedDrawingRectangleXMax = UINT16_MAX;
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rect.DrawingRectangleOriginY = 0;
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rect.DrawingRectangleOriginX = 0;
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}
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cmd_buffer->state.vb_dirty = ~0;
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cmd_buffer->state.dirty = ~0;
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cmd_buffer->state.push_constants_dirty = ~0;
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}
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