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third_party_mesa3d/src/gallium/drivers/r600/evergreen_hw_context.c

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r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
/*
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Jerome Glisse
*/
r600g: move all files from winsys/r600 into drivers/r600 Be sure to reconfigure after this commit. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-09-27 16:42:01 +02:00
#include "r600_hw_context_priv.h"
r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
#include "evergreend.h"
r600g: use Elements macro instead of manual sizeofs
2010-10-01 09:39:35 +10:00
#include "util/u_memory.h"
r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
r600g: add initial cayman acceleration support. Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-10 12:54:13 +10:00
static const struct r600_reg cayman_config_reg_list[] = {
r600g: remove unused r600_reg::flush_mask
2012-01-30 09:02:30 +01:00
{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
r600g: add initial cayman acceleration support. Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-10 12:54:13 +10:00
};
r600g: build packet header once Build packet header once and allow to add fake register support so we can handle things like indexed set of register (evergreen sampler border registers for instance. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27 11:53:34 -04:00
static const struct r600_reg evergreen_context_reg_list[] = {
r600g: remove unused r600_reg::flush_mask
2012-01-30 09:02:30 +01:00
{R_028010_DB_RENDER_OVERRIDE2, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02861C_SPI_VS_OUT_ID_0, 0, 0},
{R_028620_SPI_VS_OUT_ID_1, 0, 0},
{R_028624_SPI_VS_OUT_ID_2, 0, 0},
{R_028628_SPI_VS_OUT_ID_3, 0, 0},
{R_02862C_SPI_VS_OUT_ID_4, 0, 0},
{R_028630_SPI_VS_OUT_ID_5, 0, 0},
{R_028634_SPI_VS_OUT_ID_6, 0, 0},
{R_028638_SPI_VS_OUT_ID_7, 0, 0},
{R_02863C_SPI_VS_OUT_ID_8, 0, 0},
{R_028640_SPI_VS_OUT_ID_9, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
{R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
{R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
{R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
{R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
{R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
{R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
{R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
{R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
{R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
{R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
{R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
{R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
{R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
{R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
{R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
{R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
{R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
{R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
{R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
{R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
{R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
{R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
{R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
{R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
{R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
{R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
{R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
{R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
{R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
{R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
{R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
{R_0286C8_SPI_THREAD_GROUPING, 0, 0},
{R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
{R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
{R_0286D8_SPI_INPUT_Z, 0, 0},
{R_0286E0_SPI_BARYC_CNTL, 0, 0},
{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
{R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
{R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
{R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
{R_028ABC_DB_HTILE_SURFACE, 0, 0},
{R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
};
r600g: add initial cayman acceleration support. Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-10 12:54:13 +10:00
static const struct r600_reg cayman_context_reg_list[] = {
r600g: remove unused r600_reg::flush_mask
2012-01-30 09:02:30 +01:00
{R_028010_DB_RENDER_OVERRIDE2, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02861C_SPI_VS_OUT_ID_0, 0, 0},
{R_028620_SPI_VS_OUT_ID_1, 0, 0},
{R_028624_SPI_VS_OUT_ID_2, 0, 0},
{R_028628_SPI_VS_OUT_ID_3, 0, 0},
{R_02862C_SPI_VS_OUT_ID_4, 0, 0},
{R_028630_SPI_VS_OUT_ID_5, 0, 0},
{R_028634_SPI_VS_OUT_ID_6, 0, 0},
{R_028638_SPI_VS_OUT_ID_7, 0, 0},
{R_02863C_SPI_VS_OUT_ID_8, 0, 0},
{R_028640_SPI_VS_OUT_ID_9, 0, 0},
{R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
{R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
{R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
{R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
{R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
{R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
{R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
{R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
{R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
{R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
{R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
{R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
{R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
{R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
{R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
{R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
{R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
{R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
{R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
{R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
{R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
{R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
{R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
{R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
{R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
{R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
{R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
{R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
{R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
{R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
{R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
{R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
{R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
{R_0286C8_SPI_THREAD_GROUPING, 0, 0},
{R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
{R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
{R_0286D8_SPI_INPUT_Z, 0, 0},
{R_0286E0_SPI_BARYC_CNTL, 0, 0},
{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
{R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
{R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
{R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
{R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
{R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
{R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
{R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
{R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
{R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
{R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
{R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
{R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
{R_028ABC_DB_HTILE_SURFACE, 0, 0},
{R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
r600g: add initial cayman acceleration support. Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-10 12:54:13 +10:00
};
r600g: don't initialize the screen and winsys pointer twice
2012-01-29 23:35:10 +01:00
int evergreen_context_init(struct r600_context *ctx)
r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
{
r600g: emit the primitive type and associated regs only if the type is changed Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-10 21:59:38 +02:00
int r = 0;
r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
/* add blocks */
r600g: add support for TN (trinity) APUs Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-20 19:43:59 -04:00
if (ctx->family >= CHIP_CAYMAN)
r600g: add initial cayman acceleration support. Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-10 12:54:13 +10:00
r = r600_context_add_block(ctx, cayman_config_reg_list,
Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
r600g: build packet header once Build packet header once and allow to add fake register support so we can handle things like indexed set of register (evergreen sampler border registers for instance. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27 11:53:34 -04:00
if (r)
goto out_err;
r600g: add support for TN (trinity) APUs Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-20 19:43:59 -04:00
if (ctx->family >= CHIP_CAYMAN)
r600g: add initial cayman acceleration support. Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-10 12:54:13 +10:00
r = r600_context_add_block(ctx, cayman_context_reg_list,
Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
else
r = r600_context_add_block(ctx, evergreen_context_reg_list,
Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
if (r)
goto out_err;
r600g: add winsys support for CTL constants. These need to be emitted, we also need them to do proper vtx start, instead of abusing index offset.
2010-10-01 09:43:14 +10:00
r600g: make range/block act more like a page table only allocate the blocks ptr in the range if we ever have one, otherwise don't bother wasting the memory. valgrind glxinfo before: ==967== in use at exit: 419,754 bytes in 706 blocks ==967== total heap usage: 3,552 allocs, 2,846 frees, 3,550,131 bytes allocated after: ==5227== in use at exit: 419,754 bytes in 706 blocks ==5227== total heap usage: 3,452 allocs, 2,746 frees, 3,140,531 bytes allocate Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-12 15:01:33 +10:00
r = r600_setup_block_table(ctx);
if (r)
goto out_err;
r600g: use a hash table instead of group Instead of creating group of register use a hash table to lookup into which block each register belongs. This simplify code a bit. Signed-off-by: Jerome Glisse <jglisse@redhat.com
2010-09-28 17:37:56 -04:00
r600g: fix eg OQ properly. the context init is separate for these gpus.
2011-01-31 20:44:47 +10:00
ctx->max_db = 8;
r600g: initial evergreen support in new path This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22 17:37:30 -04:00
return 0;
out_err:
r600_context_fini(ctx);
return r;
}
r600g: implement transform feedback r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
2011-11-08 21:58:27 +01:00
void evergreen_flush_vgt_streamout(struct r600_context *ctx)
{
r600g: add multi ring support with dma as first second ring v4 We keep track of ring emission order in a stack, whenever we need to flush we empty the stack in a fifo order. There is few helpers function for bo mapping and other ring activities that will make sure that the ring stack is properly flush and submitted. v2: fix st flush path, and other flush path to properly flush all rings if necessary v3: - improve name of ring helpers - make sure that each time a cs is gona be written it endup at top of the stack to avoid any issue such as : STACK[0] = dma (withbo A,B) STACK[1] = gfx (withbo C,D) Now if code try to emit a dma command relative to bo C or D it will start writting cmd stream into the cs and once it reach the point where it adds relocation it will flush. At that point the cs will have cmd that don't have proper relocation into the relocation buffer and kernel will just refuse to run. v4: - Drop the stack idea as it turn out there is no way to use it or benefit from it. Any time the driver start command on other ring, it always need to flush the previous ring. So make code simpler by not using a stack. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-07 14:25:11 -05:00
struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
r600g: remove redundant pm4 and pm4_cdwords in r600_context These only mirrored radeon_winsys_cs.
2012-01-30 04:08:15 +01:00
r600g: use CS helpers to emit streamout state Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-18 20:21:11 +02:00
r600_write_config_reg(cs, R_0084FC_CP_STRMOUT_CNTL, 0);
r600g: remove redundant pm4 and pm4_cdwords in r600_context These only mirrored radeon_winsys_cs.
2012-01-30 04:08:15 +01:00
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */
cs->buf[cs->cdw++] = 0;
cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
cs->buf[cs->cdw++] = 4; /* poll interval */
r600g: implement transform feedback r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
2011-11-08 21:58:27 +01:00
}
void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
{
r600g: add multi ring support with dma as first second ring v4 We keep track of ring emission order in a stack, whenever we need to flush we empty the stack in a fifo order. There is few helpers function for bo mapping and other ring activities that will make sure that the ring stack is properly flush and submitted. v2: fix st flush path, and other flush path to properly flush all rings if necessary v3: - improve name of ring helpers - make sure that each time a cs is gona be written it endup at top of the stack to avoid any issue such as : STACK[0] = dma (withbo A,B) STACK[1] = gfx (withbo C,D) Now if code try to emit a dma command relative to bo C or D it will start writting cmd stream into the cs and once it reach the point where it adds relocation it will flush. At that point the cs will have cmd that don't have proper relocation into the relocation buffer and kernel will just refuse to run. v4: - Drop the stack idea as it turn out there is no way to use it or benefit from it. Any time the driver start command on other ring, it always need to flush the previous ring. So make code simpler by not using a stack. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-07 14:25:11 -05:00
struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
r600g: implement transform feedback r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
2011-11-08 21:58:27 +01:00
r600g: rework rasterizer discard for evergreen Implement it right using STRMOUT_CONFIG.RAST_STREAM. This fixes rasterizer discard with points and lines. This also adds another derived state. It's a combination of rasterizer discard and streamout enable. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-02-24 21:26:37 +01:00
if (buffer_enable_bit) {
r600g: use CS helpers to emit streamout state Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-18 20:21:11 +02:00
r600_write_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
r600_write_value(cs, S_028B94_STREAMOUT_0_EN(1)); /* R_028B94_VGT_STRMOUT_CONFIG */
r600_write_value(cs, S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit)); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
Revert "r600g: rework rasterizer discard for evergreen" I will use SX_MISC instead. This reverts commit 734792e83fdc526623d8fe0a60479648c936bd53. Conflicts: src/gallium/drivers/r600/evergreen_hw_context.c src/gallium/drivers/r600/evergreen_state.c src/gallium/drivers/r600/r600_hw_context.c src/gallium/drivers/r600/r600_pipe.h
2012-03-08 11:14:53 +01:00
} else {
r600g: use CS helpers to emit streamout state Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-18 20:21:11 +02:00
r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG, S_028B94_STREAMOUT_0_EN(0));
r600g: implement transform feedback r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
2011-11-08 21:58:27 +01:00
}
}
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