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third_party_mesa3d/src/intel/compiler/meson.build

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# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
libintel_compiler_files = files(
'brw_cfg.cpp',
'brw_cfg.h',
'brw_clip.h',
'brw_clip_line.c',
'brw_clip_point.c',
'brw_clip_tri.c',
'brw_clip_unfilled.c',
'brw_clip_util.c',
'brw_compile_clip.c',
'brw_compile_ff_gs.c',
'brw_compile_sf.c',
'brw_compiler.c',
'brw_compiler.h',
'brw_dead_control_flow.cpp',
'brw_dead_control_flow.h',
'brw_debug_recompile.c',
'brw_disasm.c',
'brw_disasm_info.c',
'brw_disasm_info.h',
'brw_eu.c',
'brw_eu_compact.c',
'brw_eu_defines.h',
'brw_eu_emit.c',
'brw_eu.h',
'brw_eu_util.c',
'brw_eu_validate.c',
intel/fs: Implement GRF bank conflict mitigation pass. Unnecessary GRF bank conflicts increase the issue time of ternary instructions (the overwhelmingly most common of which is MAD) by roughly 50%, leading to reduced ALU throughput. This pass attempts to minimize the number of bank conflicts by rearranging the layout of the GRF space post-register allocation. It's in general not possible to eliminate all of them without introducing extra copies, which are typically more expensive than the bank conflict itself. In a shader-db run on SKL this helps roughly 46k shaders: total conflicts in shared programs: 1008981 -> 600461 (-40.49%) conflicts in affected programs: 816222 -> 407702 (-50.05%) helped: 46234 HURT: 72 The running time of shader-db itself on SKL seems to be increased by roughly 2.52%±1.13% with n=20 due to the additional work done by the compiler back-end. On earlier generations the pass is somewhat less effective in relative terms because the hardware incurs a bank conflict anytime the last two sources of the instruction are duplicate (e.g. while trying to square a value using MAD), which is impossible to avoid without introducing copies. E.g. for a shader-db run on SNB: total conflicts in shared programs: 944636 -> 623185 (-34.03%) conflicts in affected programs: 853258 -> 531807 (-37.67%) helped: 31052 HURT: 19 And on BDW: total conflicts in shared programs: 1418393 -> 987539 (-30.38%) conflicts in affected programs: 1179787 -> 748933 (-36.52%) helped: 47592 HURT: 70 On SKL GT4e this improves performance of GpuTest Volplosion by 3.64% ±0.33% with n=16. NOTE: This patch intentionally disregards some i965 coding conventions for the sake of reviewability. This is addressed by the next squash patch which introduces an amount of (for the most part boring) boilerplate that might distract reviewers from the non-trivial algorithmic details of the pass. The following patch is squashed in: SQUASH: intel/fs/bank_conflicts: Roll back to the nineties. Acked-by: Matt Turner <mattst88@gmail.com>
2017-06-15 15:23:57 -07:00
'brw_fs_bank_conflicts.cpp',
'brw_fs_builder.h',
'brw_fs_cmod_propagation.cpp',
'brw_fs_combine_constants.cpp',
'brw_fs_copy_propagation.cpp',
'brw_fs.cpp',
'brw_fs_cse.cpp',
'brw_fs_dead_code_eliminate.cpp',
'brw_fs_generator.cpp',
'brw_fs.h',
'brw_fs_live_variables.cpp',
'brw_fs_live_variables.h',
'brw_fs_lower_pack.cpp',
'brw_fs_lower_regioning.cpp',
'brw_fs_nir.cpp',
'brw_fs_reg_allocate.cpp',
'brw_fs_register_coalesce.cpp',
'brw_fs_saturate_propagation.cpp',
'brw_fs_scoreboard.cpp',
'brw_fs_sel_peephole.cpp',
'brw_fs_thread_payload.cpp',
'brw_fs_validate.cpp',
'brw_fs_visitor.cpp',
'brw_inst.h',
'brw_interpolation_map.c',
'brw_ir.h',
'brw_ir_allocator.h',
'brw_ir_analysis.h',
'brw_ir_fs.h',
intel/ir: Import shader performance analysis pass. This introduces an analysis pass intended to estimate several performance statistics of the shader, including cycle count latency and throughput values, based on static modeling. It has instruction performance information more comprehensive than the current scheduling pass for all platforms between Gen4-11, and works on both the FS and VEC4 back-end. The most immediate purpose of this pass is to implement a heuristic meant to determine whether using SIMD32 dispatch for a fragment shader can be expected to help more than it hurts. In addition this will allow the effect of passes run after scheduling (e.g. the TGL software scoreboard pass and the VEC4 dependency control pass) to be visible in shader-db statistics. But that isn't the end of the story, other potential applications of this pass (not part of this MR) I've been playing around with are: - Implement a similar SIMD16 heuristic allowing the identification of inefficient SIMD16 fragment shaders. - Implement similar SIMD16 and SIMD32 heuristics for the compute shader stage -- Currently compute shader builds always use the SIMD16 shader if available and never use the SIMD32 shader unless strictly necessary, which is suboptimal under certain conditions. - Hook up to the instruction scheduler in order to improve the accuracy of its timing information. - Use as heuristic in order to drive the selection of scheduling modes (Matt was experimenting with that). - Plug to the TGL software scoreboard pass in order to implement a more effective SBID token allocation algorithm, since in general the optimal token allocation depends on the timings of all instructions in the program. - Use its bottleneck detection functionality in order to implement a heuristic computing a more optimal bound for the number of fragment shader threads executed in parallel (by adjusting the MaximumNumberofThreadsPerPSD control of 3DSTATE_PS). As a follow-up I'm planning to submit updated timing information for Gen12 platforms -- Everything else required to support Gen12 like SWSB handling is already included in this patch, but there were some IP concerns regarding the TGL timing parameters since they cannot currently be obtained with the documentation and hardware which is publicly available. The timing parameters for any previous Gen7-11 platforms can be obtained by anyone by sampling the timestamp register using e.g. shader_time, though I have some more convenient instrumentation coming up. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-03-26 14:59:02 -07:00
'brw_ir_performance.h',
'brw_ir_performance.cpp',
'brw_ir_vec4.h',
'brw_isa_info.h',
'brw_kernel.c',
'brw_lower_logical_sends.cpp',
'brw_mesh.cpp',
'brw_nir.h',
'brw_nir.c',
'brw_nir_analyze_boolean_resolves.c',
'brw_nir_analyze_ubo_ranges.c',
'brw_nir_attribute_workarounds.c',
intel/fs: clamp per vertex input accesses to patchControlPoints In a tesselation control shader where an input array is accessed using the index gl_InvocationID, we can end up accessing elements beyond the number of input vertices specified in the shader key. This happens because of the lowering in nir_lower_indirect_derefs(). This lowering will affect compact variables which happens in this case : in gl_PerVertex { vec4 gl_Position; float gl_ClipDistance[1]; } gl_in[gl_MaxPatchVertices]; The lowered code produced by NIR is somewhat ineffecient (implements a binary seach) : if (gl_InvocationID < 16) { if (gl_InvocationID < 8) { if (gl_InvocationID < 4) { vec4 vals = load_at_offset(0); value = bcsel(vals, gl_InvocationID); } else { vec4 vals = load_at_offset(4); value = bcsel(vals, gl_InvocationID - 4); } } else { if (gl_InvocationID < 12) { vec4 vals = load_at_offset(8); value = bcsel(vals, gl_InvocationID - 8); } else { vec4 vals = load_at_offset(12); value = bcsel(vals, gl_InvocationID - 12); } } } else { if (gl_InvocationID < 24) { ... } else { ... } } By default the gl_MaxPatchVertices must be set at 32 items and that's what the lowering code will use to divide the access into chunks of 4. But when running with 3 input vertices, this means we'll pull one more item than what was delivered in the shader payload. This triggers issues further down the register scheduling where the g5UD (register for the 4th item) is overwritten by a previous SEND, leading the URB read to use an invalid handle. This pass clamps any access load_per_vertex_input intrinsic vertex indice to (input_vertices - 1). Fixes issues with tests like : dEQP-VK.clipping.user_defined.clip_distance.vert_tess.* Also fixes a hang with zink/anv on : KHR-GL46.draw_elements_base_vertex_tests.AEP_shader_stages v2: Don't replace source register v3: Implement in NIR v4: Clamp per vertex array sizes in NIR (Jason) v5: Move the clamping on the intel compiler Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9749>
2021-03-25 14:53:32 +02:00
'brw_nir_clamp_per_vertex_loads.c',
'brw_nir_lower_conversions.c',
'brw_nir_lower_cs_intrinsics.c',
'brw_nir_lower_alpha_to_coverage.c',
'brw_nir_lower_intersection_shader.c',
'brw_nir_lower_ray_queries.c',
'brw_nir_lower_rt_intrinsics.c',
'brw_nir_lower_scoped_barriers.c',
'brw_nir_lower_shader_calls.c',
'brw_nir_lower_shading_rate_output.c',
'brw_nir_lower_storage_image.c',
'brw_nir_opt_peephole_ffma.c',
'brw_nir_opt_peephole_imul32x16.c',
'brw_nir_rt.h',
'brw_nir_rt.c',
'brw_nir_rt_builder.h',
'brw_nir_tcs_workarounds.c',
'brw_nir_clamp_image_1d_2d_array_sizes.c',
'brw_packed_float.c',
'brw_predicated_break.cpp',
'brw_prim.h',
'brw_private.h',
'brw_reg.h',
'brw_reg_type.c',
'brw_reg_type.h',
'brw_rt.h',
'brw_schedule_instructions.cpp',
'brw_shader.cpp',
'brw_shader.h',
'brw_simd_selection.cpp',
'brw_vec4_builder.h',
'brw_vec4_cmod_propagation.cpp',
'brw_vec4_copy_propagation.cpp',
'brw_vec4.cpp',
'brw_vec4_cse.cpp',
'brw_vec4_dead_code_eliminate.cpp',
'brw_vec4_generator.cpp',
'brw_vec4_gs_visitor.cpp',
'brw_vec4_gs_visitor.h',
'brw_vec4.h',
'brw_vec4_live_variables.cpp',
'brw_vec4_live_variables.h',
'brw_vec4_nir.cpp',
'brw_vec4_gs_nir.cpp',
'brw_vec4_reg_allocate.cpp',
'brw_vec4_surface_builder.cpp',
'brw_vec4_surface_builder.h',
'brw_vec4_tcs.cpp',
'brw_vec4_tcs.h',
'brw_vec4_tes.cpp',
'brw_vec4_tes.h',
'brw_vec4_visitor.cpp',
'brw_vec4_vs_visitor.cpp',
'brw_vec4_vs.h',
'brw_vue_map.c',
'gfx6_gs_visitor.cpp',
'gfx6_gs_visitor.h',
)
brw_nir_trig = custom_target(
'brw_nir_trig_workarounds.c',
input : 'brw_nir_trig_workarounds.py',
output : 'brw_nir_trig_workarounds.c',
command : [
prog_python, '@INPUT@', '-p', dir_compiler_nir,
],
depend_files : nir_algebraic_depends,
capture : true,
)
libintel_compiler = static_library(
'intel_compiler',
[libintel_compiler_files, brw_nir_trig, ir_expression_operation_h],
include_directories : [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel],
c_args : [no_override_init_args],
override_options: ['cpp_std=c++17'],
gnu_symbol_visibility : 'hidden',
dependencies : [idep_nir_headers, idep_mesautil],
build_by_default : false,
)
# For now this tool is only going to be used by Anv
if with_intel_clc
prog_intel_clc = executable(
'intel_clc',
['intel_clc.c'],
link_with : [
libintel_compiler, libintel_common, libintel_dev, libisl,
],
include_directories : [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel],
c_args : [pre_args, no_override_init_args],
link_args : [ld_args_build_id],
dependencies : [idep_nir, idep_clc, idep_mesautil],
native : true,
)
endif
if with_tests
test(
'intel_compiler_tests',
executable(
'intel_compiler_tests',
files(
'test_eu_compact.cpp',
'test_eu_validate.cpp',
'test_fs_cmod_propagation.cpp',
'test_fs_copy_propagation.cpp',
'test_fs_saturate_propagation.cpp',
'test_fs_scoreboard.cpp',
'test_simd_selection.cpp',
'test_vec4_cmod_propagation.cpp',
'test_vec4_copy_propagation.cpp',
'test_vec4_dead_code_eliminate.cpp',
'test_vec4_register_coalesce.cpp',
'test_vf_float_conversions.cpp',
),
ir_expression_operation_h,
include_directories : [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel],
link_with : [
libintel_compiler, libintel_common, libintel_dev, libisl,
],
override_options: ['cpp_std=c++17'],
dependencies : [idep_gtest, idep_nir, idep_mesautil],
),
suite : ['intel'],
protocol : gtest_test_protocol,
)
endif