2017-06-22 12:13:25 -07:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "nir.h"
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#include "nir_builder.h"
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/**
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* \file nir_opt_intrinsics.c
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*/
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2017-10-31 15:05:33 +01:00
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static nir_ssa_def *
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high_subgroup_mask(nir_builder *b,
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nir_ssa_def *count,
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uint64_t base_mask)
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{
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/* group_mask could probably be calculated more efficiently but we want to
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* be sure not to shift by 64 if the subgroup size is 64 because the GLSL
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* shift operator is undefined in that case. In any case if we were worried
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* about efficency this should probably be done further down because the
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* subgroup size is likely to be known at compile time.
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*/
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nir_ssa_def *subgroup_size = nir_load_subgroup_size(b);
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nir_ssa_def *all_bits = nir_imm_int64(b, ~0ull);
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nir_ssa_def *shift = nir_isub(b, nir_imm_int(b, 64), subgroup_size);
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nir_ssa_def *group_mask = nir_ushr(b, all_bits, shift);
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nir_ssa_def *higher_bits = nir_ishl(b, nir_imm_int64(b, base_mask), count);
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return nir_iand(b, higher_bits, group_mask);
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}
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2017-06-22 12:13:25 -07:00
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static bool
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opt_intrinsics_impl(nir_function_impl *impl)
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{
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nir_builder b;
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nir_builder_init(&b, impl);
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bool progress = false;
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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nir_ssa_def *replacement = NULL;
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b.cursor = nir_before_instr(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_vote_any:
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case nir_intrinsic_vote_all: {
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nir_const_value *val = nir_src_as_const_value(intrin->src[0]);
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2017-06-22 12:20:18 -07:00
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if (!val && !b.shader->options->lower_vote_trivial)
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2017-06-22 12:13:25 -07:00
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continue;
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replacement = nir_ssa_for_src(&b, intrin->src[0], 1);
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break;
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}
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case nir_intrinsic_vote_eq: {
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nir_const_value *val = nir_src_as_const_value(intrin->src[0]);
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2017-06-22 12:20:18 -07:00
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if (!val && !b.shader->options->lower_vote_trivial)
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2017-06-22 12:13:25 -07:00
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continue;
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replacement = nir_imm_int(&b, NIR_TRUE);
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break;
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}
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2017-06-30 15:07:10 -07:00
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case nir_intrinsic_ballot: {
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assert(b.shader->options->max_subgroup_size != 0);
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if (b.shader->options->max_subgroup_size > 32 ||
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intrin->dest.ssa.bit_size <= 32)
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continue;
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nir_intrinsic_instr *ballot =
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nir_intrinsic_instr_create(b.shader, nir_intrinsic_ballot);
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nir_ssa_dest_init(&ballot->instr, &ballot->dest, 1, 32, NULL);
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nir_src_copy(&ballot->src[0], &intrin->src[0], ballot);
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nir_builder_instr_insert(&b, &ballot->instr);
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replacement = nir_pack_64_2x32_split(&b,
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&ballot->dest.ssa,
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nir_imm_int(&b, 0));
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break;
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}
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2017-06-22 16:37:51 -07:00
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case nir_intrinsic_load_subgroup_eq_mask:
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case nir_intrinsic_load_subgroup_ge_mask:
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case nir_intrinsic_load_subgroup_gt_mask:
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case nir_intrinsic_load_subgroup_le_mask:
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case nir_intrinsic_load_subgroup_lt_mask: {
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if (!b.shader->options->lower_subgroup_masks)
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break;
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nir_ssa_def *count = nir_load_subgroup_invocation(&b);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_subgroup_eq_mask:
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replacement = nir_ishl(&b, nir_imm_int64(&b, 1ull), count);
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break;
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case nir_intrinsic_load_subgroup_ge_mask:
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2017-10-31 15:05:33 +01:00
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replacement = high_subgroup_mask(&b, count, ~0ull);
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2017-06-22 16:37:51 -07:00
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break;
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case nir_intrinsic_load_subgroup_gt_mask:
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2017-10-31 15:05:33 +01:00
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replacement = high_subgroup_mask(&b, count, ~1ull);
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2017-06-22 16:37:51 -07:00
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break;
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case nir_intrinsic_load_subgroup_le_mask:
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replacement = nir_inot(&b, nir_ishl(&b, nir_imm_int64(&b, ~1ull), count));
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break;
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case nir_intrinsic_load_subgroup_lt_mask:
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replacement = nir_inot(&b, nir_ishl(&b, nir_imm_int64(&b, ~0ull), count));
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break;
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default:
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unreachable("you seriously can't tell this is unreachable?");
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}
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break;
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}
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2017-06-22 12:13:25 -07:00
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default:
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break;
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}
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if (!replacement)
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continue;
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
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nir_src_for_ssa(replacement));
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nir_instr_remove(instr);
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progress = true;
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}
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}
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return progress;
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}
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bool
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nir_opt_intrinsics(nir_shader *shader)
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{
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bool progress = false;
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nir_foreach_function(function, shader) {
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2017-08-22 12:18:32 -07:00
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if (!function->impl)
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continue;
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if (opt_intrinsics_impl(function->impl)) {
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progress = true;
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nir_metadata_preserve(function->impl, nir_metadata_block_index |
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nir_metadata_dominance);
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}
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2017-06-22 12:13:25 -07:00
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}
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2017-08-22 12:18:32 -07:00
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return progress;
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2017-06-22 12:13:25 -07:00
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}
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